Andras’s Lab
(Archival from University of Massachusetts Amherst)

Publications

2011

3-D Integration Requirements for Hybrid Nanoscale-CMOS Fabrics

Pavan Panchapakeshan, Priyamvada Vijayakumar, Pritish Narayanan, Chi On Chui, Csaba Andras Moritz

in Proceedings of IEEE International Conference on Nanotechnology (IEEE NANO) , pp. 849-853 , 2011 , PDF
N3ASICs: Designing Nanofabrics with Fine-Grained CMOS Integration

Pavan Panchapakeshan, Pritish Narayanan, Csaba Andras Moritz

in Proceedings of IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch) , pp. 196-202 , 2011 , PDF
Nanoscale Application Specific Integrated Circuits

Pritish Narayanan, Jorge Kina, Pavan Panchapakeshan, Priyamvada Vijayakumar, K.-S. Shin, Mostafizur Rahman, Michael Leuchtenburg, Israel Koren, Chi On Chui, Csaba Andras Moritz

in Proceedings of IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch) , pp. 99-106 , 2011 , PDF
Biased Voting for Improved Yield in Nanoscale Fabrics

MD Muwyid Khan, Pritish Narayanan, Priyamvada Vijayakumar, Israel Koren, C. Mani Krishna, Csaba Andras Moritz

in Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT) , pp. 79-85 , 2011 , Best Paper Award , PDF
Nanoscale Application Specific Integrated Circuits

Csaba Andras Moritz, Pritish Narayanan, Chi On Chui

in Nanoelectronic Circuit Design, N. K. Jha and D. Chen, Eds. Springer New York , pp. 215-275 , 2011 , Book Chapter ,
Book

2010

Programmable Cellular Architectures at the Nanoscale

Pritish Narayanan, Teng Wang, Csaba Andras Moritz

Nano Communication Networks , Vol. 1 , No. 2 , pp. 77-85 , 2010 , PDF
Parameter Variability in Nanoscale Fabrics: Bottom-Up Integrated Exploration

Pritish Narayanan, Michael Leuchtenburg, Jorge Kina, Prachi Joshi, Pavan Panchapakeshan, Chi On Chui, Csaba Andras Moritz

in Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT) , pp. 24-31 , 2010 , PDF
Incorporating Heterogeneous Redundancy in a Nanoprocessor for Improved Yield and Performance

Priyamvada Vijayakumar, Pritish Narayanan, Israel Koren, C. Mani Krishna, Csaba Andras Moritz

in Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT) , pp. 273-279 , 2010 , PDF

2009

Heterogeneous 2-level Logic and its Density and Fault Tolerance Implications in Nanoscale Fabrics

Teng Wang, Pritish Narayanan, Csaba Andras Moritz

IEEE Transactions on Nanotechnology , Vol. 8 , Article 1 , pp. 22-30 , 2009 , PDF
Validating Cascading of Crossbar Circuits with an Integrated Device-Circuit Exploration

Pritish Narayanan, Chi On Chui, Csaba Andras Moritz

in Proceedings of IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch) , pp. 37-42 , 2009 , PDF

2008

Image Processing Architecture for Semiconductor Nanowire based Fabrics

Pritish Narayanan, Teng Wang, Michael Leuchtenburg, Csaba Andras Moritz

in Proceedings of IEEE International Conference on Nanotechnology (IEEE NANO) , pp. 677-680 , 2008 , PDF
CMOS Control Enabled Single-Type FET NASIC

Pritish Narayanan, Michael Leuchtenburg, Teng Wang, Csaba Andras Moritz

IEEE Computer Society Annual Symposium on VLSI , pp. 191-196 , 2008 , Best Paper Award , PDF, Extended PDF
NASICs: A Nanoscale Fabric for Nanoscale Microprocessors

Teng Wang, Pritish Narayanan, Michael Leuchtenburg, Csaba Andras Moritz

IEEE International Nanoelectronics Conference (INEC) , pp. 989-994 , 2008 , PDF

2007

Fault-Tolerant Nanoscale Processors on Semiconductor Nanowire Grids

Csaba Andras Moritz, Teng Wang, Pritish Narayanan, Michael Leuchtenburg, Yao Guo, Catherine Dezan, Mahmoud Bennasser

IEEE Transactions on Circuits and Systems I, Special issue on Nanoelectronic Circuits and Nanoarchitectures , Vol. 54 , No. 11 , pp. 2422-2437 , 2007 , PDF
Combining 2-level Logic Families in Grid-based Nanoscale Fabrics

Teng Wang, Pritish Narayanan, Csaba Andras Moritz

in Proceedings of IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch) , pp. 101-108 , 2007 , PDF

2006

Self-Healing Wire-Streaming Processors on 2-D Semiconductor Nanowire Fabrics

Teng Wang, Mahmoud Bennasser, Yao Guo, Csaba Andras Moritz

Nano Science and Technology Institute (NSTI) Nanotech , pp. 312 - 315 , 2006 , PDF
Combining Circuit Level and System Level Techniques for Defect-Tolerant Nanoscale Architectures

Teng Wang, Mahmoud Bennasser, Yao Guo, Csaba Andras Moritz

in Proceedings of IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch) , 2006 , PDF
Towards Defect-Tolerant Nanoscale Architectures

Csaba Andras Moritz, Teng Wang

in Proceedings of IEEE International Conference on Nanotechnology (IEEE NANO) , pp. 331-334 , 2006 , PDF

Pages